1. Field of the Invention
The present invention relates to a semiconductor device with a blind scheme that can boost its internal voltage using an external supply voltage.
2. Description of the Prior Art
FIG. 1 is a view explaining the use of an overdrive pulse generator used in a semiconductor device.
As is well known, an internal voltage generator generates a drive voltage VCORE for driving an internal circuit of the semiconductor device. If an external supply voltage VDD for driving the internal circuit is lowered and thus the driving force of the drive voltage is decreased, it is required to supplement the driving force. In this case, a circuit construction used to supplement the driving force of the voltage VCORE output from the internal voltage generator is called a blind scheme, which is composed of a pulse generator, an inverter and a PMOS transistor as illustrated in FIG. 1 in order to increase the driving force of the internal voltage VCORE.
Hereinafter, the blind scheme will be explained in more detail.
For example, it is assumed that the level of a target drive voltage VCORE is 1.6V and an external supply voltage VDD being supplied to the semiconductor device varies in the range of 1.65V˜1.95V. Typically, a semiconductor device is fabricated so as to perform a normal operation even if an external supply voltage varies in a predetermined range. However, if the external supply voltage is lowered, the driving force of an internal voltage generator that receives the external supply voltage and generates the internal voltage is decreased.
For example, the drive voltage VCORE output from the internal voltage generator when the external supply voltage level is 1.65V is much lower than the drive voltage VCORE output from the internal voltage generator when the external supply voltage level is 1.95V.
In order to solve this problem, the blind scheme is generally adopted. That is, as illustrated in FIG. 1, the circuit instantaneously raises the potential of the internal voltage VCORE up to the level of the external supply voltage VDD by turning on a PMOS transistor (i.e., driving transistor) connected to the external supply voltage VDD by applying a specified pulse signal saovd_pul to the transistor. Accordingly, the driving force of the internal voltage VCORE being applied to the internal circuit can be increased. Since it is preferable that the drive voltage VCORE has a constant voltage level, the PMOS transistor, which was turned on by the pulse signal saovd_pul, is turned off after a predetermined time to intercept the overdrive of the drive voltage VCORE. Meanwhile, if the voltage level of the external supply voltage VDD is too high, the drive voltage VCORE is overdriven and heightened over the predetermined level as shown in FIG. 2 while the PMOS transistor is turned on.
FIG. 2 is a view illustrating the change of the drive voltage VCORE output from the internal voltage generator as the external supply voltage VDD is heightened in the blind scheme in which the PMOS transistor is turned on and the external supply voltage VDD is connected to the internal circuit.
In principle, it is preferable that the drive voltage VCORE for driving the internal circuit is kept a constant level. However, as shown in FIG. 2, as the voltage level of the external supply voltage VDD is heightened, the level of the drive voltage VCORE is also heightened. This phenomenon can be prevented by adjusting the pulse width of the pulse signal saovd_pul output from the pulse generator of FIG. 1. That is, if the external supply voltage is too high, the pulse width of the pulse signal saovd_pul is shortened to reduce the turn-on time of the PMOS transistor.
However, the conventional pulse generator of FIG. 1 has the problem in that it outputs the signal saovd_pul having the constant pulse width irrespective of the voltage level of the external supply voltage, and thus the drive voltage VCORE is gradually heightened as shown in FIG. 2 if the external supply voltage is heightened.